For over two decades DRAM technology has steadily progressed to ever larger bit storage capacity per chip. Use of large conventional arrays and low current CMOS peripheral circuits has resulted in array operation becoming the primary category of electrical charge consumption per bit stored. At the same time, battery powered portable DRAM applications have become a major market in which stringent charge conservation is required. Even in non battery equipment, large array charging current causes detrimental voltage fluctuations. Thus, a clear need has emerged for techniques to reduce array charge consumption as a means to extend battery life and reduce voltage variations.
Masakazu Aoki et al. have described one such technique in a paper in the IEEE Journal of Solid State Circuits, Vol. 24, No. 5, October, 1989, pp 1206-1212, "A 1.5 V DRAM for Battery Based Applications." The method utilizes the "plate pulse" technique (See U.S. Pat. No. 4,593,382 issued Jun. 3, 1986 to Fujishima et al.) combined with a small bit line voltage swing. In conventional DRAM arrays most charge consumption is for bit line voltage swing (Vbs) and is essentially proportional to Vbs.times.Cb where Cb is the bit line capacitance. The original plate pulse technique of Fujishima, and the low charge method of Aoki, both achieve a storage node voltage swing of approximately Vbs+Vps, where Vps is the plate voltage swing. In general, DRAM data sensing signal is directly proportional to node voltage swing. Hence, Aoki et al. sacrifice substantial sense signal when they minimize bit line voltage swing in order to minimize array charge consumption. The consequences of inadequate DRAM signal are well known, and include poor product test yield and high data soft error rate. Aoki attempts to recover signal by boosting the plate voltage swing. This necessarily introduces higher voltage stress on devices and degrades overall performance unless expensive additional design and fabrication measures are taken. Therefore, a need exists for a technique which allows both low array charge consumption and high stored voltage to be obtained without boosting.
Fujishima et al. (i.e. U.S. Pat. No. 4,593,382 cited above.) also describe a commonly used dummy cell, or reference cell, in their recital of prior art (See their FIG. 1 reference numeral 3). The reference cell contains a second transistor not present in any of the memory cells. Reference cells do not store data, or binary levels, and serve only to provide a fixed reference signal for comparison with binary data signals from memory cells. Generally, DRAM reference signal is set by design so as to be midway between the high and low signals expected for memory binary data levels.